[srslte-users] Clock Rate Definitions and Overclocking

Xavier Arteaga xavier at softwareradiosystems.com
Mon Jun 25 15:33:06 UTC 2018


Hi Aygun,
The first clock rate is for cell search. The initial cell search and
selection procedure is done at a sampling rate of 1.92MHz. Once the cell is
found and selected, the sampling rate is set according to the cell
bandwidth. Since the sampling rate during cell search stage is too low
(<10MHz), the clock is set to a higher multiple.

You could try to run the lib/examples/pdsch_enodeb and the
lib/examples/pdsch_ue
examples with double sampling rate. Do they work ok?

Also, does a 50PRB cell work at double rate? You could have encountered
some USB3 throughput issues if you are using the default configuration. By
default, the over the wire format is in 16bit width integers while the ADC
has only 12bits (in B210). you could add to device_args (in ue.conf) the
parameter otw_format=sc12 for having a more compact format over the usb3.

Regards,
Xavier




On 25 June 2018 at 15:06, BALTACI, Ayguen <ayguen.baltaci at airbus.com> wrote:

> Hi mates,
>
>
>
> I am new to the forum and srsLTE. I am running srsepc + srsenb + srsue. I
> am trying to understand why USRP board is set to two different clock rates
> during initialization (see the attached image). Is 30.72 MHz clock rate
> overwritten by 23.04 MHz in the end?
>
>
>
> I want to overclock the system to measure the performance changes. Could
> you direct me how to do so? I modified the source code so that I could
> increase the clock rate from “23.04” MHz to “46.08” MHz (2nd one in the
> image) both at eNB and at UE, but then UE could not find the eNB.
>
>
>
> I look forward to your suggestions,
>
>
>
> Best Regards
>
> Aygun
>
>
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