[srslte-users] Running srsLTE at ZC702

[shahram mollahasani]

Hello
As we previously discussed, I am trying to run srsLTE on xilinx ZC702, I am
using soapysdr driver and I am using PlutoSoapy because both board use the
same chipset.
I couldn’t install the latest version of srsLTE on the ARM chipset of board
but I managed to run its previous version (18.12.0).
When I run it srsENB, I face with following output and the enb is not
discoverable by any other devices:
Built in Release mode using 18.12.0.

--- Software Radio Systems LTE eNodeB ---

Reading configuration file enb.conf...
Soapy has found device #0: device=plutosdr, driver=plutosdr, uri=local:,
set_TX_1)
Set Tx bandwidth to 0.20 MHz
TX done!
set_RX_1)
set_RX_2)
set_RX_3)
set_RX_4)
Set Rx bandwidth to 2.50 MHz
set_RX_1)
Setting up RX stream
[INFO] Using format CF32.
[INFO] Auto setting Buffer Size: 32768
[INFO] Set MTU Size: 32768
Setting up TX stream
[INFO] Using format CF32.
[INFO] Has direct TX copy: 1
soapy5
Available device sensors:

   - xadc_temp0
   - xadc_voltage0
   - xadc_voltage1
   - xadc_voltage2
   - xadc_voltage3
   - xadc_voltage4
   - xadc_voltage5
   - xadc_voltage6
   - xadc_voltage7
   - xadc_voltage8
   - adm1177_current0
   - adm1177_voltage0
   - ad9361-phy_temp0
   - ad9361-phy_voltage2
   Available sensors for RX channel 0:
   State of gain elements for Rx channel 0 (AGC supported):
   - PGA: 71.00 dB
   State of gain elements for Tx channel 0 (AGC not supported):
   - PGA: 80.00 dB
   Rx antenna set to A_BALANCED
   Tx antenna set to A

Warning burst preamble is not calibrated for device plutosdr. Set a value
manually

Receiving async metadata not supported by device. Exiting thread.
Setting frequency: DL=2685.0 Mhz, UL=2565.0 MHz
Tuned Tx to 2685.00 MHz
Tuned Rx to 2565.00 MHz
Set master clock rate to 0.00 MHz
Setting Sampling frequency 1.92 MHz
set_RX_1)
Failed to connect to MME - retrying in 10 seconds
[INFO] Auto setting Buffer Size: 32768
[INFO] Set MTU Size: 32768
set_RX_2)
set_RX_3)
set_RX_4)
Set Rx bandwidth to 2.50 MHz
set_RX_1)
set_TX_1)
Set Tx bandwidth to 0.20 MHz

==== eNodeB started ===
Type to view trace


My zc702 board is equipped with fmcomms5 or fmcomms2 frontend with ad9361
chipset. can you guide me and provide me more details about how can I
implement time-stamping in the FPGA in order to make srsenb functional in
this board?

Thank you so much for you time and your help in advance
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