[srslte-users] srsUE 20.04.1: Can't open RF frontend (NI USRP 2944 with UHD FPGA Image) - Error: Radio does not provide RF information / Error opening UHD: code 43

Marc T. m.triefelder at gmail.com
Mon Jun 1 14:24:20 UTC 2020


HI srsLTE Team and Community,

i have the issue srsUE can’t open my USRP 2944 (160MHz version). For sure i flashed there UHD Image on it. the 2944 is based on the Ettus x310 board, which should be supported actually…
When i check the device from the console with the uhd_* commands ever this seems to be fine.

But in the ue.log i can see the issue „Error: Radio does not provide RF information“ - Any Idea how to proceed in this case?


Thank you very much in advance,
Marc

Here some infos:


sml at sml-hp-b65a:~$ uhd_find_devices
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501; UHD_3.14.1.1-release
--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
    serial: 31A3xxx
    addr: 192.168.10.2
    fpga: HG
    name:
    product: X310
    type: x300
 
 
sml at sml-hp-b65a:~$ uhd_usrp_probe
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501; UHD_3.14.1.1-release
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 1472 bytes.
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D00000000000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1302 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1302 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000000)
[INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0000000000000)
  _____________________________________________________
 /
|       Device: X-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: X310
|   |   revision: 11
|   |   revision_compat: 7
|   |   product: 30806
|   |   mac-addr0: 00:80:2f:26:a4:f5
|   |   mac-addr1: 00:80:2f:26:a4:f6
|   |   gateway: 192.168.10.1
|   |   ip-addr0: 192.168.10.2
|   |   subnet0: 255.255.255.0
|   |   ip-addr1: 192.168.20.2
|   |   subnet1: 255.255.255.0
|   |   ip-addr2: 192.168.30.2
|   |   subnet2: 255.255.255.0
|   |   ip-addr3: 192.168.40.2
|   |   subnet3: 255.255.255.0
|   |   serial: 31A3xxx
|   |   FW Version: 6.0
|   |   FPGA Version: 35.1
|   |   FPGA git hash: bb85bdf
|   |   RFNoC capable: Yes
|   |
|   |   Time sources:  internal, external, gpsdo
|   |   Clock sources: internal, external, gpsdo
|   |   Sensors: ref_locked
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: A
|   |   |   ID: UBX-160 v1 (0x007a)
|   |   |   Serial: 31A0xxx
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Frontend: 0
|   |   |   |   Name: UBX RX
|   |   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: A
|   |   |   |   Name: ads62p48
|   |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
|   |     _____________________________________________________
|   |    /
|   |   |       RX Dboard: B
|   |   |   ID: UBX-160 v1 (0x007a)
|   |   |   Serial: 31A0xxx
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Frontend: 0
|   |   |   |   Name: UBX RX
|   |   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   |   Connection Type: IQ
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       RX Codec: B
|   |   |   |   Name: ads62p48
|   |   |   |   Gain range digital: 0.0 to 6.0 step 0.5 dB
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: A
|   |   |   ID: UBX-160 v1 (0x0079)
|   |   |   Serial: 31A0xxx
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Frontend: 0
|   |   |   |   Name: UBX TX
|   |   |   |   Antennas: TX/RX, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   |   Connection Type: QI
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: A
|   |   |   |   Name: ad9146
|   |   |   |   Gain Elements: None
|   |     _____________________________________________________
|   |    /
|   |   |       TX Dboard: B
|   |   |   ID: UBX-160 v1 (0x0079)
|   |   |   Serial: 31A0xxx
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Frontend: 0
|   |   |   |   Name: UBX TX
|   |   |   |   Antennas: TX/RX, CAL
|   |   |   |   Sensors: lo_locked
|   |   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   |   Connection Type: QI
|   |   |   |   Uses LO offset: No
|   |   |     _____________________________________________________
|   |   |    /
|   |   |   |       TX Codec: B
|   |   |   |   Name: ad9146
|   |   |   |   Gain Elements: None
|   |     _____________________________________________________
|   |    /
|   |   |       RFNoC blocks on this device:
|   |   |
|   |   |   * DmaFIFO_0
|   |   |   * Radio_0
|   |   |   * Radio_1
|   |   |   * DDC_0
|   |   |   * DDC_1
|   |   |   * DUC_0
|   |   |   * DUC_1
 
sml at sml-hp-b65a:~$
 
Here an except from the ue.log:

sml at sml-hp-b65a:~$ cat /tmp/ue.log
07:59:45.629027 [UE  ] [I] Built in Release mode using commit c892ae56b on branch master.
07:59:45.706804 [RF  ] [I] Configuring physical DL channel 0 with band-pass filter (0.0, 0.0)
07:59:45.706818 [RF  ] [I] Configuring physical UL channel 0 with band-pass filter (0.0, 0.0)
07:59:47.386876 [RF  ] [E] Error opening RF device
07:59:47.500038 [MAC ] [I] [    0] Resetting MAC
07:59:47.503034 [MAC ] [D] [    0] Msg3 buffer flushed
07:59:47.503049 [MAC ] [I] [    0] Logical Channel Setup: LCID=0, LCG=0, priority=0, PBR=-1, BSD=50ms, bucket_size=0
07:59:47.503054 [MAC ] [I] [    0] Logical Channel Setup: LCID=1, LCG=0, priority=1, PBR=-1, BSD=50ms, bucket_size=0
07:59:47.503062 [MAC ] [D] [    0] After MAC reset:
- lcid=0, lcg=0, prio=0, Bj=0, PBR=-1, BSD=50, buffer_len=0, sched_len=0
- lcid=1, lcg=0, prio=1, Bj=0, PBR=-1, BSD=50, buffer_len=0, sched_len=0
07:59:47.503064 [MAC ] [I] [    0] BSR:   Configured timer reTX 2560 ms
07:59:47.503071 [RLC ] [I] Added radio bearer SRB0 in Transparent Mode
07:59:47.503072 [RLC ] [I] Configured radio bearer SRB0 in Transparent Mode
07:59:47.503075 [NAS ] [I] New state DEREGISTERED
07:59:47.503108 [USIM] [I] Read Home PLMN Id=26222
07:59:47.503172 [NAS ] [I] Read GUTI from file m_tmsi: d0c2ac97, mcc: 106, mnc: 16, mme_group_id: 1, mme_code: 1
07:59:47.503180 [NAS ] [I] Read security ctxt from file .ctxt. ksi: 1, k_asme: 392be0dcb559e2f54159362e8dcd58e75e02b24e1eceb77d55a576088bc37e1c, tx_count: 4, rx_count: 4, int_alg: 2, enc_alg: 0
07:59:47.503190 [NAS ] [D] NAS encryption key - k_nas_enc
             0000: 97 80 a3 41 25 d8 57 0e f1 ca f7 06 5c 23 1b 74
             0010: 12 b0 f2 6b ed e2 62 e2 ae bb 72 12 93 12 59 29
07:59:47.503195 [NAS ] [D] NAS integrity key - k_nas_int
             0000: f9 78 39 58 42 5f d5 f6 05 d7 dc 9a 02 33 23 f7
             0010: 4d 40 56 d4 38 8d 19 37 0d fa 52 98 08 4f 9e f7
07:59:47.503205 [RRC ] [I] using srand seed of 503204
07:59:48.034353 [PHY0] [E] [    0] Error: Radio does not provide RF information
07:59:48.040594 [PHY0] [D] [    0] SYNC:  state=IDLE, tti=0
07:59:48.040605 [PHY0] [D] [    0] Sleeping
07:59:48.040691 [NAS ] [I] Saved GUTI to file m_tmsi: d0c2ac97, mcc: 106, mnc: 16, mme_group_id: 1, mme_code: 1
07:59:48.040703 [NAS ] [I] Saved security ctxt to file .ctxt. ksi: 1, k_asme: 392be0dcb559e2f54159362e8dcd58e75e02b24e1eceb77d55a576088bc37e1c, tx_count: 4, rx_count: 4, int_alg: 2, enc_alg: 0
07:59:48.040756 [MAC ] [D] [    0] Running MAC tti=0
07:59:48.040761 [MAC ] [D] [    0] Update Bj: lcid=0, Bj=0
07:59:48.040763 [MAC ] [D] [    0] Update Bj: lcid=1, Bj=0
07:59:48.040768 [MAC ] [D] [    0] RA:    INIT:   rar_window_start=-1, rar_window_length=-1
07:59:48.041618 [PHY0] [D] [    0] SYNC:  state=IDLE, tti=1
07:59:48.041626 [PHY0] [D] [    0] Sleeping
Closing log
sml at sml-hp-b65a:~$
 
 
Here is how it looks if i try to start srsue:

sml at sml-hp-b65a:~$ sudo ./srsue20.04.1 ue-v20.04-Xavier-VPN-Sky5-UHD.conf
Reading configuration file ue-v20.04-Xavier-VPN-Sky5-UHD.conf...
 
Built in Release mode using commit c892ae56b on branch master.
 
Opening 2 channels in RF device=UHD with args=recv_frame_size=9232,send_frame_size=9232
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501; UHD_3.14.1.1-release
[INFO] [LOGGING] Fastpath logging disabled at runtime.
Opening USRP channels=2, args: recv_frame_size=9232,send_frame_size=9232,master_clock_rate=23.04e6
[INFO] [X300] X300 initialization sequence...
/home/sml/srsLTE/lib/src/phy/rf/rf_uhd_imp.c.187: Error opening UHD: code 43
 
Error initializing radio.
Waiting PHY to initialize ... done!
Saving MAC PCAP file
Saving NAS PCAP file (DLT=148)
sml at sml-hp-b65a:~$

Mit freundlichen Grüßen, 
Best regards,

Marc Triefelder

E-Mail:	m.triefelder at gmail.com 





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