[srslte-users] srsRAN BER Problem with LDPC Decoding for version avx512 (layered)

[Xavier Arteaga]

Hi Leonardo,
Thanks for your interest but there are no plans to optimize the
floating-point LDPC decoder.

Kind Regards,
Xavier



On Wed, 23 Jun 2021 at 15:35, Leonardo Lo Schiavo <
leonardo.loschiavo at imdea.org> wrote:

> Hi Xavier,
>
> thanks a lot for your answer.
>
> Yes, I am expecting too that for high-order modulations 8bits LLRs close
> to zero create such problem.
> I have tried with lower modulations (BPSK) and this is not happening.
>
> Considering the better BLER performance of the float LLRs implementation,
> are you thinking of deploying an optimized version with float LLRs for
> AVX512? Thank you.
>
>
> Best Regards,
>
> Leonardo Lo Schiavo
> PhD Student @ IMDEA Networks Institute
> Leganes, Madrid, Spain
>
>
>
> On 22-06-2021 17:44, Xavier Arteaga wrote:
>
> Hi Leonardo,
> Many thanks for your email.
>
> The figure you sent made me understand the problem.
>
> I wonder if the cause is that some LLR's amplitudes are too small
> for high-order modulation.
>
> Does it happen the same if the modulation is fixed to BPSK and uses Target
> Code Rate instead of MCS?
>
> Xavier
>
>
> On Tue, 22 Jun 2021 at 15:04, Leonardo Lo Schiavo <
> leonardo.loschiavo at imdea.org> wrote:
>
>> Hi Xavier,
>>
>> yes, I have tried all the implementations and observed that those
>> implementations with 8-bits LLRs (avx512, avx2, and basic 8bits) yield the
>> issue that I mentioned in the last email. The other implementations (16bits
>> LLRs and float LLRs) do not yield such issue, and are giving much more
>> reasonable BLER performances.
>>
>> I am attaching some plots showing the avx512 layered implementation and
>> float LLRs implementation performance in terms of number of decoding
>> iterations needed to successfully decode the codeblock. White points
>> indicate that for the specific SNR-MCS pair it was not possible to decode
>> within 10 iterations and three different scaling factors were tested (0.5,
>> 0.8 and 1.0).
>>
>> I would appreciate if you had further suggestion to investigate this
>> issue. Many thanks in advance.
>>
>> Best Regards,
>>
>> Leonardo Lo Schiavo
>> PhD Student @ IMDEA Networks Institute
>> Leganes, Madrid, Spain
>>
>>
>> On 15-06-2021 09:45, Xavier Arteaga wrote:
>>
>> Hi Leonardo,
>> First of all, many thanks for sharing your findings with us.
>>
>> Have you tried if the AVX2 and generic implementations have the same BLER?
>>
>>
>> What scaling factor are you using? I observed that for 64QAM and 256QAM
>> the scaling factor had to be 0.8, see
>> https://github.com/srsran/srsRAN/blob/master/lib/src/phy/phch/sch_nr.c#L275.
>> Otherwise, code blocks could systematically fail.
>>
>> Regards,
>> Xavier
>>
>> On Mon, 14 Jun 2021 at 18:52, Leonardo Lo Schiavo <
>> leonardo.loschiavo at imdea.org> wrote:
>>
>>> Dear srsRAN community,
>>>
>>> I am writing this email to report an issue with BER performance in LDPC
>>> Decoding tests for the 8-bit version avx512 (.exe file
>>> in srsRAN/build/lib/src/phy/fec/ldpc/test/ldpc_dec_avx512_test)
>>>
>>> Basically I am generating the input LLRs for the LDPC Decoder with a
>>> MATLAB pipeline by using different parameters, namely PRB allocation, SNR
>>> and MCS.
>>> The problem is that for a given SNR value, I am getting BER=0 for higher
>>> MCS and BER > 0 for lower MCS with 10 decoding iterations, while the
>>> behaviour should be the opposite.
>>>
>>> I did the tests for both the 8-bits and 16-bits version by using the
>>> same input LLRs (just changing the quantization) and I am not getting the
>>> above issue for the 16-bits LLRs version (.exe file in
>>> srsRAN/build/lib/src/phy/fec/ldpc/test/ldpc_dec_s_test).
>>> Considering the above, I am assuming there is some kind of systematic
>>> error when decoding using the 8-bit version for the input LLRs.
>>>
>>> In order to replicate the tests, I am attaching:
>>> 1) The modified source files for 8-bit and 16-bit version
>>> 2) The input folders for 8-bit and 16-bit version (each one containing
>>> input LLRs for each codeblock and source bits per codeblock)
>>>
>>>
>>> And this is an example of a test reporting the above issue:
>>> - In srsRAN/build/lib/src/phy/fec/ldpc/test/ , run:
>>>
>>> 1) ./ldpc_dec_avx512_test -f
>>> LDPC_srsRANq_Files/Simulation_1/ldpc_BG1_K7744_PRB50_SNR20.00_mcs15_4_/ -i
>>> 10
>>> 2) ./ldpc_dec_avx512_test -f
>>> LDPC_srsRANq_Files/Simulation_1/ldpc_BG1_K8448_PRB50_SNR20.00_mcs16_4_/ -i 2
>>> 3) ./ldpc_dec_s_test -f
>>> LDPC_srsRANq16_Files/Simulation_1/ldpc_BG1_K7744_PRB50_SNR20.00_mcs15_4_/
>>> -i 2
>>> 4) ./ldpc_dec_s_test -f
>>> LDPC_srsRANq16_Files/Simulation_1/ldpc_BG1_K8448_PRB50_SNR20.00_mcs16_4_/
>>> -i 2
>>>
>>>
>>> From the above tests, only the test 1) will give a BER > 0 (even with 10
>>> iterations), which is not expected considering that with an higher MCS (16)
>>> I am getting BER = 0.
>>>
>>> Please be aware that the same issue appears also with other
>>> configurations of PRB, SNR and MCS.
>>>
>>>
>>> Could you please investigate on the above issue? Many thanks in advance.
>>>
>>>
>>> Best Regards,
>>>
>>> Leonardo Lo Schiavo
>>> PhD Student @ IMDEA Networks Institute
>>> Leganes, Madrid, Spain
>>> _______________________________________________
>>> srslte-users mailing list
>>> srslte-users at lists.softwareradiosystems.com
>>> https://lists.softwareradiosystems.com/mailman/listinfo/srslte-users
>>
>>
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